1. Field of the Invention
The present invention relates to a semiconductor device provided with a plurality of semiconductor chips and a method for production of the same. More particularly, it relates to a technique useful for reducing the size of a semiconductor device provided with a plurality of semiconductor chips and reducing the cost of the method of production of a semiconductor device.
2. Description of the Related Art
In recent years, the reduction in size of electronic apparatuses has led to a demand for a reduction in size of the semiconductor devices mounted in such electronic apparatuses. Giving one example, a semiconductor device provided with a plurality of semiconductor memory chips has been demanded to increase the storage capacity in a limited mounting region. Such a semiconductor device of the related art will be explained first with reference to FIG. 8. FIG. 8 is a sectional view of a semiconductor device of the related art.
The semiconductor device 101 shown in FIG. 8 is comprised of two semiconductor devices 108 each comprised of a semiconductor chip 106 flip-chip bonded to an interconnection substrate 109 stacked above and below each other. The interconnection substrate 109 is comprised of a polyimide film 102 and interconnection pattern 103. Among these, the polyimide film 102 is formed with through holes 102a, 102a, . . . Further, 107, 107, . . . are solder bumps. These are electrically connected with the above interconnection pattern 103 through the through holes 102a, 102a, . . . Note that the interconnection pattern 103 is comprised of copper.
Looking at the semiconductor chip 106, stud 105, 105, . . . comprised of gold are formed on its electrode terminal forming surface. These stud bumps 105, 105, . . . are electrode terminals of the semiconductor chip 106 and are electrically connected with the interconnection pattern 103 through an anisotropic conductive film 104.
As illustrated, the solder bumps 107, 107, . . . of the upper semiconductor device 108 are bonded on to the interconnection pattern 103 of the lower semiconductor device 108. Due to this, the upper and lower semiconductor devices 108 are electrically and mechanically connected. Further, by reflow of the solder bumps 107, 107, . . . of the lower semiconductor device 108 in the state with the solder bumps 107, 107, . . . abutting against the mounting board 110, the semiconductor device 101 and the mounting board 110 are electrically and mechanically connected. Further, the thickness of the lower and upper semiconductor devices 108 is about 300 xcexcm, while the overall thickness of the semiconductor device 101 is about 600 xcexcm.
According to the semiconductor device 101, since two semiconductor chips 106 are provided in the thickness direction, it is possible to reduce the mounting area compared with when arranging two semiconductor chips 106 in one plane.
Next, an explanation will be made of the method of production of this semiconductor device 101 of the related art while referring to FIGS. 9A to 9N. FIGS. 9A to 9N are sectional views of the method of production of a semiconductor device according to the related art.
First, to produce the upper semiconductor device 108, as shown in FIG. 9A, a long polyimide film 102 on which a copper foil 111 is bonded is provided.
Next, as shown in FIG. 9B, a photoresist 112 is coated on the copper foil 111.
Next, as shown in FIG. 9C, an interconnection pattern is exposed on the photoresist 112. In the FIG., 112a shows a photoresist sensitized by this exposure.
Next, as shown in FIG. 9D, the photoresist 112 is developed. Due to this, only the exposed photoresist 112a remains on the copper foil 111. The surface of the copper foil 111 at the portions not becoming interconnections is exposed.
Next, as shown in FIG. 9E, the portions of the copper foil 111 with exposed surfaces are etched. Due to this step, the parts of the copper foil 111 at the portions not becoming interconnections are removed and an interconnection pattern 103 (see FIG. 8) is formed on the polyimide film 102.
Next, as shown in FIG. 9F, the interconnection pattern 103 is made to face vertically downward and the sensitized photoresist 112a is removed.
Next, as shown in FIG. 9G, a laser beam is focused on the polyimide film 102 to form the through holes 102a, 102a, . . . (see FIG. 8). Due to the steps up to here, an interconnection substrate 109 comprised of the polyimide film 102 and the interconnection pattern 103 is completed.
Next, as shown in FIG. 9I, a film-like anisotropic conductive film 104 is bonded to the interconnection pattern 103.
Next, as shown in FIG. 9J, a semiconductor chip 106 is placed on the anisotropic conductive film 104. At this stage, the semiconductor device 106 is placed on the anisotropic conductive film by an extremely weak force. Sufficient bonding force between the semiconductor chip 106 and the interconnection substrate 109 is not yet obtained. Further, sufficient electrical connection between the stud bumps 105, 105 . . . and interconnection pattern 103 is not yet obtained either.
Next, as shown in FIG. 9K, the interconnection substrate 109 is placed on a stage 113 where a tool 114 is pressed against the semiconductor chip 106 and the anisotropic conductive film 104 is heated. Due to this, the anisotropic conductive film 104 is heated and pressed to cure, whereby a sufficient bonding force is obtained between the interconnection substrate 109 and the semiconductor chip 106. Further, due to the pressure, the portions of the anisotropic conductive film 104 sandwiched between the stud bumps 105, 105, . . . and the interconnection pattern 103 are given conductivity, whereby the semiconductor chip 106 and the interconnection substrate are electrically connected. Below, the step of heating and pressing the anisotropic conductive film in this way will be called the xe2x80x9cmain press bonding stepxe2x80x9d.
When this main press bonding step is finished, the step shown in FIG. 9L is performed. In this step, solder bumps 107, 107, . . . are placed on the parts of the interconnection pattern 103 exposed from the through holes 102a, 102a . . . 
In the above figures, the portion corresponding to a single semiconductor device 108 is shown, but in practice, as shown in FIG. 9M, a plurality of semiconductor devices 108 are formed on a long polyimide film 102.
Next, as shown in FIG. 9N, the polyimide film 102 is cut to separate the plurality of semiconductor devices 108 into individual pieces.
Finally, each of the individual pieces of the semiconductor devices 108 is inspected to determine if it satisfies predetermined specifications for electrical characteristics.
Due to this, the upper semiconductor device 108 shown in FIG. 8 is completed.
The main points of the above production process may be summarized as in FIG. 10. FIG. 10 is a flow chart of the main points of the method of production of a semiconductor device of the related art.
As shown at the left in FIG. 10, the production process of the upper semiconductor device 108 is comprised of the following six steps:
Step P1: Bonding of anisotropic conductive film 104 (step of FIG. 9I)
Step P2: Mounting of semiconductor chip 106 (step of FIG. 9J)
Step P3: Main press bonding (step of FIG. 9K)
Step P4: Mounting of solder bumps 107 (step of FIG. 9L)
Step P5: Separation into individual pieces (step of FIG. 9N)
Step P6: Inspection
Further, the lower semiconductor device 108 (see FIG. 8), as shown at the right side of FIG. 10, is produced by the same six steps as the production process of the upper semiconductor device 108. When the lower semiconductor device 108 is completed, it is stacked together with the already completed upper semiconductor device 108 to complete the semiconductor device 101 shown in FIG. 8.
Summarizing the problems to be solved by the invention, for further reduction of the size of electronic apparatuses, it is desirable that the thickness of the semiconductor device mounted in it be made as small as possible.
As shown in FIG. 8, however, in the semiconductor device 101 of the related art, two interconnection substrates 109 are provided in the thickness direction. Therefore, the thickness of the semiconductor device 101 ends up becoming greater by the amount of the thickness of the interconnection substrate 109.
Further, comparing the heat expansion coefficients of an interconnection substrate 109 comprised mainly of a polyimide plastic and a semiconductor element 106 comprised mainly of silicon, the heat expansion coefficient of the interconnection substrate 109 is far greater. Therefore, under situations where the semiconductor device 101 is heated, such as when reflowing the solder bumps 107, 107, . . . , stress occurs in the interconnection substrate 109 due to the difference in heat expansion coefficients between the interconnection substrate 109 and the semiconductor chip 106 and the interconnection substrate 109 ends up warping.
If the interconnection substrate 109 warps in this way, however, the stud bumps 105, 105 . . . end up separating from the anisotropic conductive film 104 and the reliability of electrical connection between the semiconductor chip 106 and the interconnection substrate 109 ends up falling.
On the other hand, it is desirable that the number of steps in the method of production of a semiconductor device be made as small as possible to reduce the manufacturing cost of the semiconductor device.
As shown in FIG. 10, however, in the past, each of the upper semiconductor device 108 and lower semiconductor device 108 were produced by exactly the same process, so the same process had to be performed twice to produce a single semiconductor device 101 and therefore the number of steps ended up becoming larger. Specifically, the six steps from step P1 to P6 shown in FIG. 10 had to be performed for each of the upper and lower semiconductor devices 108 and consequently a total of 12 steps (=six stepsxc3x972) ended up becoming necessary.
A first object of the present invention is to provide a semiconductor device thinner than the past and improved in reliability of electrical connection between semiconductor chips and an interconnection substrate.
A second object of the present invention is to provide a method for production of the above semiconductor device by fewer steps than in the past.
To achieve the first object, according to a first aspect of the present invention, there is provided a semiconductor device comprising an insulating plastic film formed with through holes; an interconnection pattern formed on one surface of said plastic film and covering openings of said through holes at least at said one surface; a first semiconductor chip flip-chip bonded on said interconnection pattern so as to be electrically connected with said interconnection pattern; a second semiconductor chip flip-chip bonded on the other surface of said plastic film so as to be electrically connected with said interconnection pattern through said through holes; and external connection terminals electrically connected with said interconnection pattern.
Preferably, said first semiconductor chip and said second semiconductor chip are arranged shifted from each other so that they do not completely overlap.
More preferably, a stress-cancellation plate is affixed at the region where the first semiconductor chip and the second semiconductor chip do not overlap on either surface of said plastic film.
Preferably, a first semiconductor chip and second semiconductor having the same functions and same electrode terminal array are used.
Preferably, a reinforcement plate is affixed to an edge region of one of the surfaces of said plastic film.
To achieve the second object, according to a second aspect of the present invention, there is provided a method of production of a semiconductor device comprising the steps of forming an interconnection pattern on one surface of an insulating plastic film; forming in said plastic film through holes having openings covered by said interconnection pattern; forming a first anisotropic conductive film on said interconnection pattern; forming a second anisotropic conductive film on the other surface of the plastic film and inside said through holes after forming said interconnection pattern; preliminarily press bonding one surface of a first semiconductor chip provided with projecting electrode terminals on said first anisotropic conductive film; preliminarily press bonding one surface of a second semiconductor chip provided with projecting electrode terminals on said second anisotropic conductive film so that said electrode terminals are inserted in said through holes through said second anisotropic conductive film; and simultaneously pressing the other surfaces of the first semiconductor chip and said second semiconductor chip in a state with said first anisotropic conductive film and said second anisotropic conductive film heated so as to electrically connect the electrode terminals of the first semiconductor chip and second semiconductor chip and said interconnection pattern for main press bonding.
According to the semiconductor device of the present invention, provision is made of an insulating plastic film formed with through holes. On one surface of the plastic film is formed an interconnection pattern covering the openings at least at that one surface. Further, a first semiconductor chip is flip-chip bonded on the interconnection pattern so as to be electrically connected with the interconnection pattern.
On the other hand, a second semiconductor chip is flip-chip bonded to the other surface of the plastic film so as to be electrically connected with the interconnection pattern through the through holes. The outside connection terminals are electrically connected with the interconnection pattern. By this structure, the interconnection substrate is comprised by the plastic film and interconnection pattern, but only one interconnection substrate is provided in the thickness direction of the semiconductor device. Therefore, compared with the conventional example where two interconnection substrates are provided in the thickness direction of the semiconductor device, the thickness of the semiconductor device can be made smaller.
Further, in the above structure, since the first semiconductor chip and the second semiconductor chip are provided at both surfaces of the plastic film, the stresses occurring at the two surfaces of the plastic film due to the difference in heat expansion coefficients of the plastic film and semiconductor chips are canceled out. Therefore, even under conditions where the semiconductor device is heated, since the interconnection substrate does not warp as in the past, the reliability of electrical connection between the semiconductor chips and the interconnection substrate is improved.
Note that the first semiconductor chip and the second semiconductor chip may be arranged shifted from each other so as not to completely overlap. If this is done, the portions of the interconnection pattern electrically connected with the first semiconductor chip and the portions electrically connected with the second semiconductor chip are arranged separated from each other, so these portions will no longer short-circuit.
Further, when the first semiconductor chip and the second semiconductor chip are arranged shifted from each other in this way, a stress-cancellation plate may be provided. This stress-cancellation plate is affixed on one surface of the plastic film in a region where the first semiconductor chip and second semiconductor chip do not overlap. Since the two semiconductor chips do not overlap in that region, the stresses acting from the semiconductor chips to the plastic film remain without being canceled out. Therefore, if a stress-cancellation plate is affixed in that region, the stress acting from the stress-cancellation plate to the plastic film and the stresses remaining without being canceled out are canceled out and warping of the interconnection substrate in that region is suppressed.
Further, if a first semiconductor chip and a second semiconductor chip having the same functions and same electrode terminal array are used the design of the interconnection pattern is simplified. This is because if semiconductor chips having the same electrode terminal array are used, there is an axis of symmetry on the plastic film and the same electrode terminals of the two semiconductor chips become positioned line symmetrically with respect to that axis, so it becomes possible to connect the same electrodes linearly. Note that the ability to connect the same electrode terminals in this way is due to the use of two semiconductor chips with the same functions.
Further, it is possible to affix a reinforcement plate to the edge region of one surface of the plastic film. Due to this reinforcement plate, the strength of the semiconductor device is raised.
Further, the method of production of the semiconductor device according to the present invention includes a main press bonding step where the first semiconductor chip and the second semiconductor chip are electrically connected simultaneously to the interconnection pattern. By simultaneously electrically connecting the two semiconductor chips to the interconnection pattern in this way, the number of steps of the process of production of the semiconductor device is reduced, so the manufacturing cost of the semiconductor device is lowered.